With a view to achieving higher integration and higher performance of a semiconductor device, an SGT (Surrounding Gate Transistor) has been proposed which is a vertical transistor comprising a pillar-shaped semiconductor layer formed on a surface of a semiconductor substrate, and a gate formed to surround a sidewall of the pillar-shaped semiconductor layer (as disclosed, for example, in Patent Document 1: JP 2-188966A). In the SGT, a source, a gate and a drain are arranged in a vertical direction, so that an occupancy area can be significantly reduced as compared with a conventional planar transistor.
In cases where an LSI (large-scale integration) circuit is made up using an SGT, it is essential to employ an SRAM comprising a combination of a plurality of SGTs, as a cache memory for the LSI circuit. In recent years, there is an extremely strong need for increasing a capacity of an SRAM to be mounted on an LSI circuit. Thus, in the SGT-based LSI circuit, it is also essential to achieve an SRAM having a sufficiently-small cell area.
FIG. 24(a) and FIG. 24(b) are, respectively, a top plan view and a sectional view of a CMOS 6T-SRAM disclosed as one embodiment in Patent Document 2 (JP 7-99311A), wherein an SRAM cell comprises six transistors each designed using an SGT. With reference to FIGS. 24(a) and 24(b), a structure of the SRAM cell will be described below. A bit line, a ground line GND, and a power supply potential line Vcc, are formed by an N+ diffusion layer (601a, 601b), an N+ diffusion layer 602, and a P+ diffusion layer 603. Six pillar-shaped silicon layers are formed on the diffusion layers to constitute two access transistors 610a, 610b each operable to allow access to a memory cell, two driver transistors 611a, 611b each operable to drive the memory cell, and two load transistors 612a, 612b each operable to supply electric charges to the memory cell. Further, a gate (604a, 604b, 604c, 604d) is formed to surround each of the pillar-shaped silicon layers. A storage node is made up of an interconnection layer (607a, 607b). In each of the transistors constituting the SRAM cell, a source, a gate and a drain are vertically formed on and along the pillar-shaped silicon layer, so that the SRAM cell can be designed to have a sufficiently-small cell area.
Patent Document 1: JP 2-188966A
Patent Document 2: JP 7-99311A (paragraph [0051], FIG. 75)
Patent Document 3: JP 2000-12705A
In reality, the above SRAM cell involves the following problem. In the SRAM discloses in the Parent Document 2, each of the power supply potential line 603 and the ground line 602 in an SRAM cell array can be formed at a level of minimum size so as to achieve a sufficiently-small cell area. However, the power supply potential line 603 and the ground line 602 are formed by the P+ diffusion layer and the N+ diffusion layer, respectively. Thus, if each of the power supply potential line 603 and the ground line 602 is formed at a level of minimum size, a resistance thereof will be extremely increased, which makes it impossible to ensure a stable operation of the SRAM. Conversely, if the size of each of the power supply potential line 603 and the ground line 602 is increased so as to allow the SRAM to stably operate, the SRAM cell area will be increased.
As an SRAM capable of achieving a greater reduction in SRAM cell area than the CMOS 6T-SRAM, a Loadless 4T-SRAM (the Patent Document 3: JP 2000-12705A) has been proposed. FIG. 1 shows an equivalent circuit of a Loadless 4T-SRAM cell. The Loadless 4T-SRAM cell comprises total four transistors consisting of two PMOS access transistors each operable to access to the memory cell, and two NMOS driver transistors each operable to the memory cell.
As one example of an operation of the memory cell in FIG. 1, a data holding operation under a condition that data “L” is stored in a storage node Qa1, and data “H” is stored in a storage node Qb1, will be described below. During the data holding operation, each of a word line WL1 and two bit lines BL1, BLB1 is driven to an “H” potential. A threshold voltage of the access transistor (Qp11, Qp21) is set to be less than that of the driver transistor (Qn11, Qn21), and an OFF-leak current of the access transistor is set to be greater (e.g., on average, about 10 to 1000 times greater) than a leak current of the driver transistor. Thus, an OFF-leak current flows from the bit line BLB1 to the storage node Qb1 through the access transistor Qp21, so that the “H” level in the storage node Qb1 is held. Meanwhile, the “L” level in the storage node Qa1 is stably held by the driver transistor Qn11.
Even in SGT-based SRAMs, the Loadless 4T-SRAM can achieve a smaller SRAM cell area as compared with the CMOS 6T-SRAM.
In view of the above circumstances, it is an object of the present invention to provide an SGT-based Loadless 4T-SRAM capable of achieving a sufficiently-small SRAM cell area, while ensuring a sufficient operation margin thereof.